Synchronous dynamic random access memory (“SDRAM”) is dynamic random access memory (“DRAM”) that is synchronized with a respective computer's system bus. In particular, SDRAM has a synchronous interface that waits for a system clock signal before responding to control inputs. The clock signal is used to drive an internal finite state machine that pipelines incoming commands. The data storage area is divided into several banks, allowing the memory device to work on several memory access commands at a time. This allows for higher data access rates than with asynchronous DRAM memory chips.
SDRAM is widely used in computers and mobile computing devices, including mobile phones, computing tablets, global positioning systems, etc. Several generations of double data rate (“DDR”) SDRAM have entered the mass market, including DDR1, DDR2, DDR3, and DDR4. The Joint Electron Device Engineering Council (“JEDEC”), an independent semiconductor engineering trade organization and standardization body, issues specification requirements for each of the generations of DDR SDRAM. The specifications for the above mentioned generations and any future generations of DDR SDRAM are incorporated herein by reference.
Mobile DDR (also known as mDDR, low power DDR, or LPDDR) is a type of double data rate synchronous DRAM for mobile smart phones, tablets, and other mobile computing devices. The first generation low power DDR (sometimes referred to as, “LPDDR1”) is a slightly modified form of DDR SDRAM, with several changes to reduce overall power consumption. Most significantly, the supply voltage is reduced from 2.5V to 1.8V. Additional savings come from temperature-compensated refresh, partial array self-refresh, and a deep power down mode, which sacrifices memory contents. Later generations of LPDDR have been developed and marketed, including LPDDR2, LPDDR3, etc. The specifications for the above mentioned generations of LPDDRn and any future generations of LPDDRn are incorporated herein by reference.
Rambus' R+DDRn family of memory interface solutions provide improvements to LPDDRn devices. For instance, memory devices that implement R+LPDDR3 offer reduced power consumption, increased data rates, and improved cost-effectiveness. By incorporating innovations such as flex phase timing adjustment circuits, output driver calibration, on die termination (“ODT”) calibration, and low-overhead multi-modal functionality, R+DDRn physical layers (“PHYs”) deliver improved margin and flexibility to allow system designers to optimize a computer system for their unique requirements.
The R+LPDDR3 memory PHY is optimized for mobile applications and is fully compliant with the LPDDR3 specification. When paired with R+LPDDR3, the memory device can support data rates of up to 2400 Mbps with a roadmap up to 3200 Mbps, and is capable of reducing active memory system power by up to 25% and active DRAM power by up to 30%. The R+LPDDR3 solution can also enable a significantly improved thermal profile and an increased battery life for the end device that houses the R+LPDDR3 memory device. As a consequence of the improved the thermal profile, the end device is able to run the memory system at peak bandwidth for longer periods of time which translates to better overall performance in the end device.
In order to take advantage of any one of the types of DDR SDRAM technologies, the end device must be specifically engineered to use one of the types of DDR memory configurations. This can be expensive for DDR SDRAM manufactures since each different system may use a different type of DDR SDRAM. For instance, one system may use LPDDR2, another system might use LPDDR3, yet another system might use R+LPDDR3, and further yet another system might use LPDDR4. This would mean that a DDR SDRAM manufacturer would need to make various memory devices to match each of the different systems.
Therefore, there exists a need to provide a new memory device that supports multiple DDR SDRAM memory configuration modes. Furthermore, there exists a need to provide methods for selecting one of the memory configuration modes to operate the memory device. Other refinements for a memory device to conserve power and to prevent transistor latch up that can apply to any IO specification and configuration are also desirable.